Forming conductors on integrated circuits to provide signal lines is well known. More recently, due to smaller lithographies allowing signal lines to be placed closer together, cross-talk and parasitic capacitance between lines has become more predominant.
Referring to FIG. 1, there is shown a perspective view depicting an exemplary embodiment of a non-tapered signal line 103 of the prior art, which may be disposed in a conductive layer (“metal layer”) of an integrated circuit. Non-tapered signal line 103 is conventionally disposed in a horizontal orientation, latitudinal or longitudinal orientation, with respect to an integrated circuit, where via interconnects are formed to interconnect horizontally oriented signal lines or devices of different layers, as is known.
On either side of non-tapered signal line 103 are non-tapered shielding lines 129. Examples of non-tapered shielding lines 129 may be ground lines or a direct current source voltage (e.g., Vcc) lines, namely, an alternating current (“AC”) ground line. Conventionally, non-tapered shielding lines 129 and non-tapered signal line 103 are formed with at least approximately the same depth or height 102. Notably, conventionally, non-tapered signal line 103 is formed with at least approximately a same width 101 along its extent, and non-tapered shielding lines 129 are conventionally formed with approximately a same width 130 along its extent. However, conventionally non-tapered shielding lines 129 are formed with a minimum possible width, which may be substantially smaller than width of non-tapered signal lines 103. Furthermore, conventionally, non-tapered shielding lines 129 are at least approximately spaced a same spacing distance 131 from non-tapered signal line 103. In other words, non-tapered lines 103 and 129 are conventionally designed to have a same sidewall height 102 and spatial separation 131 from beginning to end, though, when formed, some variation may result.
Referring to FIG. 2, there is shown a cross-sectional view depicting an exemplary embodiment of non-tapered signal lines 103 disposed in a portion of an integrated circuit 100 of the prior art. For example, a conductive material may be used to form non-tapered signal lines 103 and a same or different conductive material may be used to form interconnect lines or via interconnects 121. Though a dual damascene flow is shown for forming signal lines 103 with via interconnects 121, it should be appreciated that via interconnects 121 and non-tapered signal lines 103 may be separately formed.
Interlayer dielectric layers 110 and 111 may be formed for defining trenches and vias, as is known. Thus, it should be appreciated that a sidewall parasitic capacitance exists between sidewalls of non-tapered signal lines 103 and non-tapered shielding lines 129 with interlayer dielectric 110, and any intervening barrier layer 131 sandwiched between such sidewalls. Accordingly, sidewall parasitic capacitance will be substantially the same along the extent of non-tapered signal line 103.
Conventional thought is that parasitic capacitance is a problem, namely, because it adds capacitance, C, and thus increases the resistance-capacitance, RC, time constant for signal propagation. In other words, parasitic capacitance delays signal propagation.
Accordingly, because parasitic capacitance is a fact of life in integrated circuit design, it would be both desirable and useful to re-arrange parasitic capacitances in order to improve integrated circuit performance.